An important aspect in many manufacturing processes is the testing of the resulting products. Testing is used to verify that the manufactured products function and operate properly and perform in accordance with the specifications set forth by the product design. There are often pluralities of tests which may be performed on the product or products at different points or stages in the manufacturing process. For example, after a particular sub-assembly of a product is manufactured, there may be tests performed to verify the specific functions of the sub-assembly prior to its incorporation into an overall final product. In addition to or oftentimes as a preferred alternative to separate testing of the sub-assemblies or sub-components, there may be tests performed on the final overall completed product including testing of the one or more sub-components thereof after the final step of the manufacturing/assembling process.
In order to meet an ever-increasing demand of consumers for the latest high technology products, manufacturers are forced to constantly design and deliver these new products to the marketplace in an ever decreasing time span. Techniques that shorten the time needed to bring a product to market can provide a competitive advantage over competitors who do not have access to such techniques. Consequently, any such techniques or mechanisms to shorten the time-to-market are desirable and may be readily accepted by manufacturers. Shortening the total time required to adequately test the functionality of the manufactured products is one way to decrease the time required and can thus be one if not the most time critical element in bringing a new product to market. As such, the overall test time may typically be a function of one or more factors, e.g.: (1) the run time of the test, i.e., the time it takes to actually perform a particular test on the device, and (2) the test development or set-up time, i.e., the time it takes to configure, verify and set-up the test equipment to perform the test. Thus, in order to decrease the total test time, it is desirable to find ways to shorten either or both of the run time and/or the set-up times of the tests.
Heretofore, integrated circuit (IC) and/or system on a chip (SOC) and/or multi-chip module (MCM) devices have been tested and verified using a variety of testing methods. In some examples, IC and/or SOC devices have been tested and verified to be defect free using functional test vectors, i.e., electrical stimuli, such as those applied to the IC and/or SOC by the use of automated test equipment (ATE), which stimulate and verify the IC/SOC device functionality at the pin-level of the device. A practical advantage to the utilization of such equipment, ATE, for testing ICs and/or SOCS, is in some embodiments, the use of multiple independent ports of a single ATE which will allow independent control of multiple independent ports for parallel or concurrent testing of discrete portions of the ICs or often more especially the SOCs or like devices. In such cases, discrete pins (or pads) are discretely assigned to particularly defined ports of the ATE. Then the ATE can perform discrete test patterns concurrently via the separate ports.
Among other advantages, concurrent testing of this sort has enabled parallel testing of multiple intellectual property (IP) blocks within each device. Likewise, such a test system allows for concurrent testing of any number of on-chip functions. For example, such a system can test multiple logic, embedded memory and/or analog or digital IP blocks in parallel rather than sequentially. The only fundamental requirement, addressed in the design and test set-up phases, is that the discrete IP blocks and/or other logic on the IC or SOC (system-on-a-chip) device be isolated as designed so they are independently accessible, observable, and controllable and may thus be assigned to separate, discrete ports during the test set-up phase. Testing of this sort of SOC is allowed by the per-port architecture of the ATE which supports independent testing of the assigned blocks including such independent test parameters as period, timing, levels, pattern and sequencing.
Note, SOCs and likewise MCMs may be considered special kinds of ICs wherein SOCs and MCMs are devices which may contain an assortment of one or more circuit features such as intellectual property (IP) blocks in SOCs and/or multiple chips in MCMs. These may then include, for example, logic cores, memories, embedded processors, and/or a range of mixed-signal and RF cores to support voice, video, audio and/or data communications. Thus, SOCs and MCMs may represent a sort of IC integration, where stand-alone IC chipsets are merged into a few or even into a single SOC or MCM. To save on development costs, several SOC or MCM vendors today are creating converged ICs that include a wide range of computational, communication, and/or entertainment functionality. Such devices may require many or all of these capabilities because their jobs may include obtaining data and/or executable code from or through various communication methods and/or protocols, decoding that data and/or code and then displaying, distributing and/or storing that data and/or executing the code to operate in accordance therewith.
However, given that these converged SOCs and/or MCMs may be highly elastic in the capabilities they will provide, the exact test requirements for each SOC or MCM is a function of the IP blocks or individual pre-existing chips integrated therein. Also, these converged SOCs and MCMs will typically require a full gamut of testing capabilities; from RF and mixed signal to high-speed digital, memory, and scan test. To test the various IP blocks using traditional ATE equipment has often involved the use of sequential testing. Parallel or concurrent test strategies, on the other hand, were made available by the use of a plurality of otherwise separate ports or channels in the ATE. A port is a connection on or from the ATE to a collection of one or more pins in/on the IC/SOC. Independent tests may then be performed concurrently or in parallel using separate ports so long as the pins are properly and separately assigned to separate ports. For example, a certain first set of pins on an SOC may be dedicated to a particular IP core on the SOC, and a second set of pins may similarly be separately dedicated to a second particular IP core on the same SOC; then, each of these sets of pins may then be assigned to separate ports on the ATE, and thus provide for separate and parallel, i.e., non-sequential testing of those two IP cores. This can then reduce test time; e.g., the same number of tests can be run at a reduced time so long as some of the tests are run concurrently. Reduced test time assumes however, that the pins are properly assigned to the appropriate ATE ports during test set-up.
As utilized herein, the term device is intended hereafter to include and refer to a chip or an IC and/or an SOC and/or an MCM as well, and thus these are also intended to be used interchangeably, with the exception of those specific references to the term SOC where it may be discretely distinct from any ordinary chip or IC. Moreover, the term device is also intended to refer to and encompass a multi-chip module (MCM) (also known as an MCU, or multi-chip unit) which is a device having two or more chips or ICs (or SOCS, or any combination thereof) disposed on a single or common substrate.